The present invention relates to a method and/or apparatus for implementing optical receivers generally and, more particularly, to a method and/or apparatus for electronically tuning the transimpedance response of an optical receiver.
Referring to FIG. 1, a circuit 10 implementing a conventional singled-ended common-base input stage followed by an RC power splitter is shown. The circuit 10 is shown receiving an input from a photo-detector 12. The circuit 10 provides a DC balanced output to be directly coupled to a successive differential output stage. The RF (or high speed signal path) goes through a series capacitor CSERIES.
A practical limit to wide band applications is imposed by the capacitor CSERIES, especially for 40 Gb/s SONET OC-768 applications. A large value of the capacitor CSERIES is used to obtain low frequency gain response. However, a small-low parasitic capacitor CSERIES is used to obtain a resonance free bandwidth up to 40 GHz. This competing requirement is typically not resolved without compromising either lower or higher frequency response. Such a limitation is fundamentally caused by the capacitor CSERIES in series with the high speed signal line. However, elimination of the capacitor CSERIES results in gain loss across the entire band due to the voltage division caused by the resistor RSERIES of the power splitter.
The common-base input allows high input overload capability. A monolithic RC power splitter is used to obtain DC balance fed to the differential output OUT1 and OUT2. The capacitor CSERIES is implemented in-line with the RF signal path. Such a monolithic implementation can cause parasitic self resonance problems in-band, especially for 40 Gb/s applications. A smaller value for the capacitor CSERIES can inhibit the onset of parasitic effects and can result in impairment of low frequency performance. The capacitor CSERIES can also cause group delay dispersion due to self-resonances within a 100 kHz-40 GHz band.
Referring to FIG. 2, a circuit 20 illustrates a conventional differential common-base input stage followed by an emitter follower stage. The circuit 20 is shown receiving an input from a photo-detector 22. When driven single-endedly by the photo-detector 22, a DC offset imbalance occurs at the outputs of the follower stage. Such a DC offset imbalance can create duty-cycle distortion and inter-symbol interference (ISI) as well as common-mode bias problems for a successive differential output amplifier stage.
The common-base input of the circuit 20 allows high input overload capability. The differential common-base input enables differential DC balanced outputs OUT1 and OUT2 (under no power drive) which can be directly coupled to a differential output buffer stage. With increasing optical input power illuminating the photo-detector 22, the DC levels can become unbalanced leading to duty cycle distortion.
In order to satisfy the need for high current overload capability, the common-base transimpedance pre-amplifier topologies shown in FIG. 1 and FIG. 2 are commonly used. Common-base input stages are capable of high input currents, but offset distortion still arises when converting the signal from single-ended to complementary outputs. Offset distortion tends to increase as optical power is increased. Conventional approaches for achieving the single-end to complementary conversion for a common-base input stage use RC power splitters that may not be amenable to higher frequency monolithic implementations due to self resonances of the components. Differentially balanced CB topologies driven single-endedly do not generally address offset imbalance due to single-ended input operation.
Referring to FIG. 3, a diagram of an input waveform that may be presented to the circuit 10 or the circuit 20 is shown. The input waveform may be illustrated with 3 mA pxe2x80x94p overload current excitation when operating at 40 Gb/s. FIG. 4 illustrates a DC offset unbalance at the output of the common-base differential stage. FIG. 5 illustrates complementary outputs having severe duty cycle distortion.
It would be desirable to provide a transimpedance amplifier particularly suitable for high speed (e.g., 40 Gb/s) optical receiver applications that exhibits low duty cycle distortion under high overload conditions.
The present invention concerns an apparatus comprising a common-base amplifier circuit and a control circuit. The amplifier circuit may be configured to generate an output signal having a transimpedance bandwidth in response to an input signal. The control circuit may be (i) coupled between the output signal and the input signal and (ii) configured to provide a DC offset adjustment by providing current steering at the input signal.
The objects, features and advantages of the present invention include providing an amplifier that may (i) provide wide bandwidth transimpedance response that may be suitable for next generation (e.g., 40 Gb/s and greater) optical receiver applications, (ii) provide transimpedance bandwidth tuneability performance to accommodate for (a) process variations in the photo-detector, (b) process variations of the amplifier, and (c) module assembly manufacturing variations (wirebond variations, etc.), (iii) provide a circuit that may accommodate post assembly tuning of the transimpedance response, (iv) provide an amplifier with high dynamic range that may be suitable for 40 Gb/s optical receiver applications, (v) provide overload performance for state of the art 40 Gb/s diode responsivities of  greater than 0.9 A/W when overload current requirements of  greater than 2.85 mA pxe2x80x94p are needed, (vi) comply with an overload specification more aggressive than those imposed by common 10 Gb/s PIN diode technologies, and/or (vii) provide an approach for reducing waveform distortion in a transimpedance amplifier such as overshoot (ringing) and duty cycle distortion.